Posts tagged ‘Semiconductor’

Engineers Demonstrate First Room-Temperature Semiconductor Source Of Coherent Terahertz Radiation

Engineers and applied physicists from Harvard University have demonstrated the first room-temperature electrically-pumped semiconductor source of coherent Terahertz (THz) radiation, also known as T-rays. The breakthrough in laser technology, based upon commercially available nanotechnology, has the potential to become a standard Terahertz source to support applications ranging from security screening to chemical sensing.Spearheaded by research associate Mikhail Belkin and Federico Capasso, Robert L. Wallace Professor of Applied Physics and Vinton Hayes Senior Research Fellow in Electrical Engineering, both of Harvard’s School of Engineering and Applied Sciences (SEAS), the findings will be published in the May 19 issue of Applied Physics Letters. The researchers have also filed for U.S. patents covering the novel device.

 

Using lasers in the Terahertz spectral range, which covers wavelengths from 30 to 300å, has long presented a major hurdle to engineers. In particular, making electrically pumped room-temperature and thermoelectrically-cooled Terahertz semiconductor lasers has been a major challenge. These devices require cryogenic cooling, greatly limiting their use in everyday applications.

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Signal Conditioning Issues

In industrial applications, a digital-to-analog (D-to-A) interface may be rather straightforward but the analog-to-digital (A-to-D) converter (ADC) can be a challenge. The capacitive input stage of both delta-sigma and successive approximation register (SAR) interfaces used for the ADC requires signal capture within a limited time frame. An improper signal chain can cause ringing and oscillation and result in inaccurate readings. However, this is just one of many factors to consider when selecting an ADC.

Signal Chain

High-performance ADCs convert the output of an analog sensor to a digital format for a microcontroller or digital signal processor. The selection of the ADC must be part of a systems approach. “When somebody starts a design, you start with the sensor, you see what kind of output impedance it has and you choose an amplifier and resistors around the amplifier and you choose that configuration based on your sensor,” says Chuck Sins, applications engineer, National Semiconductor. “Based on the accuracy of your sensor and what you are ultimately trying to achieve, then I choose the resolution of the ADC.”

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Mems- Micro-Electro-Mechanical Systems

Mems- Micro-Electro-Mechanical Systems from Universal Semiconductor, Inc. USI offers rugged, miniature, and high sensitivity MEMS process capability for manufacture of sensors, transducers, switches, mirrors, and many diverse special custom designed products that go into wide ranging applications from medical to aerospace.

MEMS Design and Manufacturing Services The MEMS integrated sensor chip can be readily combined with a signal conditioning circuitry chip for amplification, offset compensation, linearity improvement, and temperature compensation. All parameters for amplification, offset compensation, linearity improvement, and temperature compensation are stored in an internal EEPROM. No additional components required, simplifies incorporation in to existing systems.

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Directed Self-Ordering Of Organic Molecules For Electronic Devices

A simple surface treatment technique demonstrated by a collaboration between researchers at the National Institute of Standards and Technology (NIST), Penn State and the University of Kentucky potentially offers a low-cost way to mass produce large arrays of organic electronic transistors on polymer sheets for a wide range of applications including flexible displays, “intelligent paper” and flexible sheets of biosensor arrays for field diagnostics. In a paper posted this week, the team describes how a chemical pretreatment of electrical contacts can induce self-assembly of molecular crystals to both improve the performance of organic semiconductor devices and provide electrical isolation between devices.

Organic electronic devices are inching towards the market. Compounds with tongue-twisting names like “5,11-bis(triethylsilylethynyl) anthradithiophene” can be designed with many of the electrical properties of more conventional semiconductors. But unlike traditional semiconductors that require high-temperature processing steps, organic semiconductor devices can be manufactured at room temperature. They could be built on flexible polymers instead of rigid silicon wafers. Magazine-size displays that could be rolled up or folded to pocket size and plastic sheets that incorporate large arrays of detectors for medical monitoring or diagnostics in the field are just a couple of the tantalizing possibilities.

One unsolved problem is how to manufacture them efficiently and at low cost. Large areas can be coated rapidly with a thin film of the organic compound in solution, which dries to a semiconductor layer. But for big arrays like displays, that layer must be patterned into electrically isolated devices. Doing that requires one or more additional steps that are costly, time-consuming and/or difficult to do accurately.

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All-Nanotube Transistor Radio Developed

Carbon nanotubes have a sound future in the electronics industry, say researchers who built the world’s first all-nanotube transistor radios to prove it.

The nanotube radios, in which nanotube devices provide all of the active functionality in the devices, represent “important first steps toward the practical implementation of carbon-nanotube materials into high-speed analog electronics and other related applications,” said John Rogers, a Founder Professor of Materials Science and Engineering at the University of Illinois.

Rogers is a corresponding author of a paper that describes the design, fabrication and performance of the nanotube-transistor radios, which were achieved in a close collaboration with radio frequency electronics engineers at Northrop Grumman Electronics Systems in Linthicum, Md.

The paper has been accepted for publication in the Proceedings of the National Academy of Sciences, and is to be published in PNAS Online Early Edition next week.

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NIST Develops Test Method For Key Micromechanical Property

Engineers and researchers designing and building new microelectromechanical systems (MEMS) can benefit from a new test method developed at the National Institute of Standards and Technology (NIST) to measure a key mechanical property of such systems: elasticity. The new method determines the “Young’s modulus” of thin films not only for MEMS devices but also for semiconductor devices in integrated circuits.

Since 1727, scientists and engineers have used Young’s modulus as a measure of the stiffness of a given material. Defined as the ratio of stress (such as the force per unit area pushing on both ends of a beam) to strain (the amount the beam is deflected), Young’s modulus allows the behavior of a material under load to be calculated. Young’s modulus predicts the length a wire will stretch under tension or the amount of compression that will buckle a thin film. A standard method to determine this important parameter — a necessity to ensure that measurements of Young’s modulus made at different locations are comparable — has eluded those who design, manufacture and test MEMS devices, particularly in the semiconductor industry.

A team at NIST recently led the effort to develop SEMI Standard MS4-1107, “Test Method for Young’s Modulus Measurements of Thin, Reflecting Films Based on the Frequency of Beams in Resonance.” The new standard applies to thin films (such as those found in MEMS materials) that can be imaged using an optical vibrometer or comparable instrument for non-contact measurements of surface motion. In particular, measurements are obtained from resonating beams — comprised of the thin film layer — that oscillate out-of-plane. The frequency at which the maximum amplitude (or velocity) of vibration is achieved is a resonance frequency, which is used to calculate the Young’s modulus of the thin film layer. The group also developed a special Web-based “MEMS calculator”  (http:// www.eeel.nist.gov/812/test-structures/MEMSCalculator.htm) that can be used to determine specific thin film properties from data taken with an optical interferometer.

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Nanoscale Details Of Photolithography Process In Semiconductor Manufacturing Revealed

Gaithersburg, MD — Scientists at the National Institute of Standards and Technology (NIST) have made the first direct measurements of the infinitesimal expansion and collapse of thin polymer films used in the manufacture of advanced semiconductor devices. It’s a matter of only a couple of nanometers, but it can be enough to affect the performance of next-generation chip manufacturing. The NIST measurements, detailed in a new paper,* offer a new insight into the complex chemistry that enables the mass production of powerful new integrated circuits. The smallest critical features in memory or processor chips include transistor “gates.” In today’s most advanced chips, gate length is about 45 nanometers, and the industry is aiming for 32-nanometer gates. To build the nearly one billion transistors in modern microprocessors, manufacturers use photolithography, the high-tech, nanoscale version of printing technology. The semiconductor wafer is coated with a thin film of photoresist, a polymer-based formulation, and exposed with a desired pattern using masks and short wavelength light (193 nm). The light changes the solubility of the exposed portions of the resist, and a developer fluid is used to wash the resist away, leaving the pattern which is used for further processing.

Exactly what happens at the interface between the exposed and unexposed photoresist has become an important issue for the design of 32-nanometer processes. Most of the exposed areas of the photoresist swell slightly and dissolve away when washed with the developer. However this swelling can induce the polymer formulation to separate (like oil and water) and alter the unexposed portions of the resist at the edges of the pattern, roughening the edge. For a 32-nanometer feature, manufacturers want to hold this roughness to at most about two or three nanometers.

Industry models of the process have assumed a fairly simple relationship in which edge roughness in the exposed “latent” image in the photoresist transfers directly to the developed pattern, but the NIST measurements reveal a much more complicated process. By substituting deuterium-based heavy water in the chemistry, the NIST team was able to use neutrons to observe the entire process at a nanometer scale. They found that at the edges of exposed areas the photoresist components interact to allow the developer to penetrate several nanometers into the unexposed resist. This interface region swells up and remains swollen during the rinsing process, collapsing when the surface is dried. The magnitude of the swelling is significantly larger than the molecules in the resist, and the end effect can limit the ability of the photoresist to achieve the needed edge resolution. On the plus side, say the researchers, their measurements give new insight into how the resist chemistry could be modified to control the swelling to optimal levels.

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